A variety of techniques have been developed to increase the overall processing speed of computer systems. Vast improvements in integrated circuit processing technologies have contributed to the ability to increase computer processing speeds and memory capacity, thereby contributing to the overall improved performance of computer systems. The ability to produce integrated circuits with deep sub-micron features enables the number of electrical components, such as capacitors, per integrated circuit to also increase. Emerging technologies, such as 3D-stacked memory, has also led to an exponential increase in the potential memory capacity a computer system can offer. However, the amount of memory devices and the exponentially increasing memory capacities are ineffective if the performance of the device suffers due to an ill-organized cache architecture.
Caches are widely utilized to bridge memory latency and improve performance of a computer system. Today static random-access memory (SRAM) based caches are most commonly used to design last-level caches. However, SRAM is generally expensive in terms of power consumption and circuit area. An alternative to SRAM-based caches is caches built using low-cost memory technologies typically reserved for main memory, including dynamic random-access memory (DRAM), high bandwidth memory (HBM), phase-change memory (PCM), etc. These memory types are capable of high capacities and high overall bandwidths; however, the tradeoff is processing at a high latency.
In the following description, the use of the same reference numerals in different drawings indicates similar or identical items. Unless otherwise noted, the word “coupled” and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise noted any description of direct connection implies alternate embodiments using suitable forms of indirect electrical connection as well.